1. Field of the Invention
This invention relates generally to the field of computing technology and more particularly concerns the boot sequence of a computer system which prepares the system for loading an operating system.
2. Description of the Related Art
Perhaps the most revolutionary development in recent years to impact the human condition has been the technological advances in the personal computer. The processor speed and memory capacity of today's generation of workhorse computers far exceed those of previous generations and are increasing exponentially as technology rapidly develops.
An important aspect of computer systems today is a boot sequence, or initialization routine, whereby a computer system is prepared for operation by ultimately loading an operating system (i.e. during booting). Initialization generally involves ascertaining the availability and status of hardware devices and resetting counters, switches, registers or other storage contents to starting values to prepare the system for data processing. To this end, and as generally introduced in prior art FIG. 1(a), a simplified computer system 10 has a mother board 12 upon which resides, among other components, a CPU 14, system RAM 16 and system ROM BIOS 18. These three components communicate with one another along a host bus 13 which is in communication with a PCI bus 20 via a bus bridge 15 that manages communication between the buses, performs deadlock resolution, and updates memory accesses as is well known in the art. During initialization, a program counter informs CPU 14 of the address of the next instruction needed for processing. Here, the address is the beginning of a boot program permanently stored in a set of ROM chips that comprise part of system ROM BIOS 18 and contain the computer's basic input/output system (BIOS).
Upon execution of the system ROM BIOS, the ROM BIOS boot program invokes a series of system checks to ascertain the location, number and identity of various devices associated with computer system 10. To accomplish this, CPU 14 transmits signals over the system's PCI bus 20 to ensure they are functioning properly. Mother board 12 includes a plurality of expansion slots (i.e., PCI slots that are connected to the PCI bus 20), each of which may contain a controller, such as controllers 22a, 22b . . . 22n. Each of these controllers may be, by way of example only, a display adapter, a hard disc controller, a floppy disc controller, a network adapter, an SCSI card or other similar device. For computer systems operating in a windows environment, many of these devices are of the plug and play (PNP) type. Physically connected to each of controllers 22a . . . 22n is a selected number of peripheral devices (PD) 28, or drives, such as a bootable CD ROM driver, a container (CNTR) or a pass-through (PT) driver. Each peripheral device 28 is interconnected to its associated controller 22a, 22b . . . 22n by an appropriate interface (i.e., such as a SCSI bus), 26a, 26b . . . 26n, respectively. Also associated with each of the controllers is the controller's firmware code, which is referred to as the Option ROM BIOS, such as Option ROM BIOS 24a, 24b . . . 24n.
The initialization routine incorporates each of the controller's Option ROM BIOS code into the system RAM 16 as part of the system's overall BIOS and memory configuration. As shown in FIG. 1(b), each Option ROM BIOS 25 includes a first memory allocation 30 for the controller's BIOS initialization code and a second memory allocation 32 for the controller's run time code, which is essentially an INT13 call allowing computer system 10 to communicate with the controller's peripheral device(s). Allocated within system RAM 16 is a memory block 16a of approximately 128 k that is commonly allocated at hexadecimal addresses C000h, through DFFFh, as shown in FIG. 1(c). It is this 128 k of memory within system RAM 16 that is reserved for Option ROM BIOS 24a, 24b . . . 24n.
As shown in FIG. 1(d), it is not uncommon for the Option ROM BIOS associated with the computer system's video card to require approximately 32 k of memory block 16.sub.a between addresses C000h through C800h, thereby leaving a remainder of only 96 k between addresses C800h and DFFFh allocated for containing the Option ROM BIOS of the remaining controllers. In many situations, this is insufficient memory capacity in which to load the Option ROM BIOS of the remaining controllers. For example, and as also illustrated in FIG. 1(d), it is possible for the run time code of the second controller, being that part of the Option ROM BIOS (which does not include the BIOS initialization code), to require 36 k of memory, thereby leaving 60 k allocated for the Option ROM BIOS of controller 22b. In cases where option ROM BIOS (initialization and run time) is a size of 64 k for controller 22b, the system will not have enough memory space to accommodate this controller code, and hence will choke on it. This scenario is further complicated by the fact that newer chip sets manufactured by the Intel Corporation of Santa Clara, Calif., only allocate memory within system RAM 16 in 16 k blocks, as opposed to the 2 k block memory allocations prevalent in older Intel chip sets. So, for example, even if the Option ROM BIOS for controller 22b required 50 k of memory, an amount less than the available 60 k remaining in system RAM 16 after loading controller 24a, it could not be loaded within memory block 16a because the chip set would effectively require a minimum of 64 k of available space.
The inability to load the Option ROM BIOS of each of the controllers as shown in the scenario above, which represents one of many possible such scenarios, ultimately renders the computer system unable to boot from any controller card who's Option ROM BIOS has not been loaded into system RAM. This not only hinders the versatility of the computer system by jeopardizing the user's ability to designate a desired boot drive, but it can also cause a system failure if the controller whose Option ROM BIOS has been loaded does not contain the operating system.
In view of the foregoing, what is needed is a new and improved methodology for use in a computer system to optimize versatility and efficiency by allowing the computer system to boot from any controller, irrespective of the number of controllers present in the system without choking the available memory. To this end, it is also desirable to accomplish such versatility within the memory confinements of today's computer systems, as discussed hereinabove.